1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a method of forming trench transistors and shallow trench isolation structures using a single trench formation process step.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are thereafter interconnected by a conductor which extends over a dielectric which separates or "isolates" the individual devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS processes involve oxidizing field regions between devices. The oxide grown in field regions is termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process". Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep sub-micron MOS technologies. The shallow trench process is better suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.05 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width.
Despite its advantages over LOCOS, the conventional trench isolation process requires dedicated photolithography and dry etch steps to define the isolation trenches prior to the transistor fabrication sequence. These processing steps increase manufacturing costs by heightening the demand for typically scarce photolithography and plasma etch resources. Therefore, it would be desirable if the cost imposed by the addition of a trench formation process sequence enabled additional processing benefits.
The operating characteristics of a transistor fabricated with standard metal-oxide-semiconductor (MOS) integrated circuit techniques are a function of the transistor's dimensions. In particular, the transistor's source-to-drain current (I.sub.ds) is proportional to the ratio of the transistor's width (W) to the transistor's length (L). For a given transistor width W and a given biasing condition (e.g. V.sub.G =3V, V.sub.D =3V, and V.sub.S =0V), I.sub.ds is maximized by minimizing the transistor length L. Minimizing transistor channel length improves the speed of integrated circuits, which comprise a large number of individual transistors, because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from an device operation standpoint. In addition, minimizing the transistor length L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and, with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The main limitation of minimum device size in a conventional transistor fabrication process is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist layer. The patterned mask transmits the illumination source radiation onto selected areas of the photoresist layer to reproduce the mask pattern in the photoresist layer. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system. The diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleighs criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criteria is satisfied when the 2d=0.61 .lambda./NA. Where 2d is the separation distance of the two images, .lambda. is the wavelength of the energy source, and NA is the numerical aperture of the lens.
As process technologies approach and surpass the resolvable limits of photolithography aligners, semiconductor manufacturers are typically forced to implement alternative techniques to achieve adequate resolution of the minimum features. Unfortunately, the conventional alternatives involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. For example, it is typically necessary to upgrade photolithography aligners or abandon the optical alignment equipment entirely and replace it with advanced lithography equipment such as e-beam or x-ray lithography equipment to adequately resolve features in the deep sub-micron range (i.e. &lt;0.5 .mu.m). The cost associated with replacing or upgrading photolithography equipment can be prohibitive due to the capital required to purchase and install the improved equipment and the extensive costs associated with qualifying the new equipment for production worthiness and training production and maintenance personnel in the operation and care of the new equipment.
In addition, conventional transistor fabrication processes, in which the transistor gate is formed above the semiconductor substrate, result in a non-planar surface upon which subsequent processing layers must be fabricated. The non-planar surface increases the difficulty of subsequent processing. In particular, photolithography resolution is negatively affected by variations in the thickness of the photoresist layer across non-planar regions or "steps" in the underlying substrate. Photoresist line width variations are common over steps in the underlying substrate primarily due to standing wave effects and light scattering at the steps caused by diffraction and reflection effects. Moreover, it is difficult to fabricate the shallow source/drain junction depth that is required to minimize short channel effects in deep submicron transistor technologies. This is especially true with respect to p-channel devices where the source/drain impurity typically comprises boron which is known to have a high diffusion coefficient. It would therefore be desirable to implement a transistor fabrication process that enables the reduction of the minimum transistor channel length, improves the planarity of the wafer surface upon which the post-fabrication processing sequence occurs, integrates nicely with a shallow trench isolation process, and facilitates the formation of shallow source/drain junctions.